1. Field of the Invention
This invention relates to a timing circuit suitable for use in a DRAM or the like.
2. Description of the Related Art
A timing circuit has heretofore been known which has an inverter electrically connected to an input terminal, a RC delay circuit electrically connected to the output of the inverter and a two-input NAND circuit whose inputs are respectively electrically connected to the output of the RC delay circuit and the output of the inverter. A signal outputted from the timing circuit immediately changes from an L to an H levels in response to a change of an input signal from an L to an H levels. Further, the output signal also changes from an H to an L levels after a predetermined period has elapsed since the change of the input signal from the H to the L levels. Namely, the timing circuit outputs a signal having a pulse broader wider than that of the input signal.
However, although described in detail later, the conventional timing circuit outputs a signal which changes from an H to an L levels after a predetermined period has elapsed since a change of glitch noise from an H to an L levels even when the glitch noise is inputted to the input terminal. Namely, the timing circuit serves so as to broaden even a pulse width of the glitch noise. Accordingly, a circuit supplied with the output signal referred to above was apt to cause a malfunction.